1. Field of Invention
The present invention relates to a fabrication method for a semiconductor. More particularly, the present invention relates to a method for fabricating a dual damascene.
2. Description of Related Art
As integration for integrated circuits (IC) increases, an interconnect design with more than two layers has gradually become the method of choice in many IC processes. An inter-metal dielectric (IMD) layer is often used to isolate between metal layers, while a conducting wire, which connects the top metal layer and the bottom metal layer, is known as a via in the semiconductor industry. The dual damascene process is a technology which involves simultaneously forming the via and the interconnect.
Conventionally, the IMD layer of the dual damascene is made of silicon oxide (SiO.sub.x) with a dielectric constant of about 4. To satisfy the need for fast development of the semiconductor industry, where RC delay is reduced to improve the data transfer rate, fluorinated silicon glass (FSG) with a lower dielectric constant (about 3.5) is currently used to replace silicon oxide as a material for forming the IMD layer.
FSG not only reduces the capacitance between interconnects, but is also compatible with the copper interconnect process. A silicon oxy-nitride layer or a silicon nitride layer, which would serve as an etching stop layer and copper diffusion barrier layer, respectively, is usually formed before formation of a FSG layer in the dual damascene process. As a result, a problem such as surface sensitivity, otherwise known as surface dependency, occurs when the FSG layer is formed on the silicon oxy-nitride layer or the silicon nitride layer, and has a serious effect on the subsequent semiconductor process.
FIG. 1 is a schematic, cross-sectional diagram illustrating a conventional process for fabricating dual damascene. First of all, a silicon nitride layer or silicon oxy-nitride layer 101 and a planarized fluorinated silicon glass (FSG) layer 102 are formed in sequence on a substrate 100. A silicon nitride layer or silicon oxy-nitride layer 104 which serves as an etching stop layer and/or diffusion barrier layer is formed on the FSG layer 102, wherein the silicon nitride layer or silicon oxy-nitride layer 104 has an opening. Another FSG layer 106 is then formed on the silicon nitride layer or silicon oxy-nitride layer 104. In order to form a trench 108 and a via opening 110 which expose a conducting layer (not shown), the FSG layers 102 and 106 are etched respectively according to the required pattern of the metal conducting wire. So, an opening constituted of the trench 108 and via opening 110 is formed in the presence of the etching stop layer 104. The trench 108 and the via opening 110 are then filled with a conducting layer 109. Hence, the dual damascene process is the process which forms both the trench 108 and the via opening 110 as described.
However, FSG may not have a uniform deposition thickness on the chip surface and there may be a problem of surface sensitivity when the FSG layer is deposited on the silicon nitride layer or silicon oxy-nitride etching stop layer. As the FSG layer does not have a uniform thickness, the subsequent semiconductor process is affected.